Record Details

Negative bias temperature instability in CMOS devices

DSpace at IIT Bombay

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Field Value
 
Title Negative bias temperature instability in CMOS devices
 
Creator MAHAPATRA, S
ALAM, AA
KUMAR, PB
DALEI, TR
VARGHESE, D
SAHA, D
 
Subject mosfet
nbti
interface traps
bulk traps
parameter instability
reaction-diffusion model
hydrogen diffusion
 
Description This paper reviews the experimental and modeling efforts to understand the mechanism of Negative Bias Temperature Instability (NBTI) in p-MOSFETs, which is becoming a serious reliability concern for analog and digital CMOS circuits. Conditions for interface and bulk trap generation and their dependence on stress voltage and oxide field, temperature and time are discussed. The role of inversion layer holes, hot-holes and hot-electrons are also discussed. The recovery of generated damage and its bias, temperature and AC frequency dependence are discussed. The degradation and recovery is modeled using the standard Reaction-Diffusion theory, and some unique data scaling features are pointed out. The impact of gate-oxide nitridation is also reviewed.
 
Publisher ELSEVIER SCIENCE BV
 
Date 2011-10-22T12:17:47Z
2011-12-15T09:10:55Z
2011-10-22T12:17:47Z
2011-12-15T09:10:55Z
2005
 
Type Article; Proceedings Paper
 
Identifier MICROELECTRONIC ENGINEERING,80,114-121
0167-9317
http://dx.doi.org/10.1016/j.mee.2005.04.053
http://dspace.library.iitb.ac.in/xmlui/handle/10054/14896
http://hdl.handle.net/100/1733
 
Source 14th Biennial Conference on Insulating Films on Semiconductors,Leuven, BELGIUM,JUN 22-24, 2005
 
Language English