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Performance trade-offs by the use of high-K gate dielectrics in sub 100 nm channel length MOSFETs
DSpace at IIT Bombay
View Archive Info| Field | Value | |
| Title |
Performance trade-offs by the use of high-K gate dielectrics in sub 100 nm channel length MOSFETs
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| Creator |
SHARMA, S
RAO, VR |
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| Description |
High-k gate dielectrics are currently under extensive investigation, for use in sub quarter micron MOSFETs, to suppress the gate leakage current. However, the performance degradation because of the increased fringing field effects, due to the higher physical thickness of a high-K dielectric in relation to the channel length, has attracted considerable attention. Tn this work, we show a way to confine the fringing field effects in a sub 100nm channel Length MOSFET by using a low-K material as a spacer dielectric. We present extensive device simulations on a 70 nm channel length MOSFET with different high-k gate and low-K spacer materials, and analyze the resulting performance issues.
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| Publisher |
SPIE-INT SOC OPTICAL ENGINEERING
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| Date |
2011-10-23T20:13:41Z
2011-12-15T09:10:57Z 2011-10-23T20:13:41Z 2011-12-15T09:10:57Z 2000 |
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| Type |
Proceedings Paper
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| Identifier |
PROCEEDING OF THE TENTH INTERNATIONAL WORKSHOP ON THE PHYSICS OF SEMICONDUCTOR DEVICES, VOLS I AND II,3975,896-899
0-8194-3601-1 0277-786X http://dspace.library.iitb.ac.in/xmlui/handle/10054/15224 http://hdl.handle.net/100/1758 |
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| Source |
10th International Workshop on the Physics of Semiconductor Devices (IWPSD 99),NEW DELHI, INDIA,DEC 14-18, 1999
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| Language |
English
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