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Optimization and realization of sub 100nm channel length lateral asymmetric channel P-MOSFETS

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Title Optimization and realization of sub 100nm channel length lateral asymmetric channel P-MOSFETS
 
Creator HEMKAR, M
VASI, J
RAO, VR
CHENG, B
WOO, JCS
 
Description Lateral Asymmetric Channel (LAC) p-MOSFETs with channel lengths down to 100 nm are optimized, fabricated and characterized as part of this study. We show, for the first time, the results of extensive experiments done on LAC p-MOSFETs, including the effect of tilt angle of V-T adjust implant, on the device performance. Both uniform and asymmetric devices are fabricated on the same wafer for more accurate comparison.
 
Publisher SPIE-INT SOC OPTICAL ENGINEERING
 
Date 2011-10-23T20:21:12Z
2011-12-15T09:10:57Z
2011-10-23T20:21:12Z
2011-12-15T09:10:57Z
2000
 
Type Proceedings Paper
 
Identifier PROCEEDING OF THE TENTH INTERNATIONAL WORKSHOP ON THE PHYSICS OF SEMICONDUCTOR DEVICES, VOLS I AND II,3975,584-587
0-8194-3601-1
0277-786X
http://dspace.library.iitb.ac.in/xmlui/handle/10054/15225
http://hdl.handle.net/100/1763
 
Source 10th International Workshop on the Physics of Semiconductor Devices (IWPSD 99),NEW DELHI, INDIA,DEC 14-18, 1999
 
Language English