Record Details

Electrically induced junction MOSFET for high performance sub-50nm CMOS technology

DSpace at IIT Bombay

View Archive Info
 
 
Field Value
 
Title Electrically induced junction MOSFET for high performance sub-50nm CMOS technology
 
Creator DIXIT, A
DUSANE, RO
RAO, VR
 
Subject channel
 
Description Degrading of short-channel effects (SCE) e.g. Drain-Induced-Barrier-Lowering (DIBL), charge-sharing etc., as CMOS devices are scaled into the sub-50nm regime, is a major roadblock for ULSI technologies. This problem can be circumvented to some extent by a proper scaling of MOSFET vertical dimensions (junction depths, oxide thickness etc.). In this work we propose a novel implementation of an electrically induced junction (EJ) MOSFET. An EJ-MOSFET is different from conventional CMOS device in that the gate voltage electrically induces the shallow source-drain extensions (SDEs). In such a device the SDEs are underneath the gate and contain low-doped regions of opposite conductivity as that of deep source-drain (S/D). In order to turn ON the device, a voltage is applied at the gate of EJ-MOSFET device, such that these low doped regions below poly-Si gate get inverted and serve as SDEs. Consequently, the effective channel length in this condition is the distance between these low-doped regions. On the contrary, at any gate voltage less than that required for inverting these regions, no SDEs are induced, and the effective channel length is equal to the physical separation between the deep S/D junctions.
 
Publisher MATERIALS RESEARCH SOCIETY
 
Date 2011-10-23T09:47:14Z
2011-12-15T09:11:05Z
2011-10-23T09:47:14Z
2011-12-15T09:11:05Z
2002
 
Type Proceedings Paper
 
Identifier SILICON MATERIALS-PROCESSING, CHARACTERIZATION AND RELIABILITY,716,305-310
1-55899-652-4
0272-9172
http://dspace.library.iitb.ac.in/xmlui/handle/10054/15093
http://hdl.handle.net/100/1841
 
Source Symposium on Silicon Materials held at the 2002 MRS Spring Meeting,SAN FRANCISCO, CA,APR 01-05, 2002
 
Language English