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Effective dielectric thickness scaling for high-K gate dielectric MOSFETs

DSpace at IIT Bombay

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Title Effective dielectric thickness scaling for high-K gate dielectric MOSFETs
 
Creator BHUWALKA, KK
MOHAPATRA, NR
NARENDRA, SG
RAO, VR
 
Description It has been shown recently that the short channel performance worsens for high-K dielectric MOSFETs as the physical thickness to the channel length ratio increases, even when the effective oxide thickness (EOT) is kept identical to that of SiO2. In this work we have systematically evaluated the effective dielectric thickness for different K-gate to achieve targeted threshold voltage (V-t), drain-induced barrier lowering (DIBL) and I-on/I-off ratio for different technology generations down to 50 nm using 2-Dimensional process and device simulations. Our results clearly show that the oxide thickness scaling for high-K gate dielectrics and SiO2 follow different trends and the fringing field effects must be taken into account for estimation of effective dielectric thickness when SiO2 is replaced by a high-K dielectric.
 
Publisher MATERIALS RESEARCH SOCIETY
 
Date 2011-10-23T10:01:25Z
2011-12-15T09:11:05Z
2011-10-23T10:01:25Z
2011-12-15T09:11:05Z
2002
 
Type Proceedings Paper
 
Identifier SILICON MATERIALS-PROCESSING, CHARACTERIZATION AND RELIABILITY,716,215-219
1-55899-652-4
0272-9172
http://dspace.library.iitb.ac.in/xmlui/handle/10054/15096
http://hdl.handle.net/100/1845
 
Source Symposium on Silicon Materials held at the 2002 MRS Spring Meeting,SAN FRANCISCO, CA,APR 01-05, 2002
 
Language English