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Effect of technology scaling on MOS transistor performance with high-K gate dielectrics

DSpace at IIT Bombay

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Title Effect of technology scaling on MOS transistor performance with high-K gate dielectrics
 
Creator MOHAPATRA, NR
DESAI, MP
NARENDRA, SG
RAO, VR
 
Subject kappa
 
Description The impact of technology scaling on the MOS transistor performance is studied over a wide range of dielectric permittivities using two-dimensional (2-D) device simulations. It is found that the device short channel performance is degraded with increase in the dielectric permittivity due to an increase in dielectric physical thickness to channel length ratio. For K-gate greater than K-si, we observe a substantial coupling between source and drain regions through the gate dielectric. We provide extensive 2-D device simulation results to prove this point. Since much of the coupling between source and drain occurs through the gate dielectric, it is observed that the overlap length is an important parameter for optimizing DC performance in the short channel MOS transistors. The effect of stacked gate dielectric and spacer dielectric on the MOS transistor performance is also studied to substantiate the above observations.
 
Publisher MATERIALS RESEARCH SOCIETY
 
Date 2011-10-23T10:32:00Z
2011-12-15T09:11:06Z
2011-10-23T10:32:00Z
2011-12-15T09:11:06Z
2002
 
Type Proceedings Paper
 
Identifier SILICON MATERIALS-PROCESSING, CHARACTERIZATION AND RELIABILITY,716,133-138
1-55899-652-4
0272-9172
http://dspace.library.iitb.ac.in/xmlui/handle/10054/15101
http://hdl.handle.net/100/1852
 
Source Symposium on Silicon Materials held at the 2002 MRS Spring Meeting,SAN FRANCISCO, CA,APR 01-05, 2002
 
Language English