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High field stressing effects in JVD nitride capacitors

DSpace at IIT Bombay

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Title High field stressing effects in JVD nitride capacitors
 
Creator MANJULARANI, KN
RAO, VR
VASI, J
 
Subject border traps
interface
oxides
radiation
bias
 
Description The performance of Jet Vapour Deposited (JVD) Silicon Nitride devices under high field stressing is reported in this paper. Border traps were generated when n-substrate capacitors were stressed with negative gate voltages. Also, an increase in bulk positive charges as well as interface trap density was observed. These results indicate that stressing under negative gate voltages may cause long term reliability problems in Metal-Nitride-Semiconductor (MNS) devices'. Stressing with positive gate voltage, however, does not show any significant degradation.
 
Publisher SPIE-INT SOC OPTICAL ENGINEERING
 
Date 2011-10-23T22:06:26Z
2011-12-15T09:11:11Z
2011-10-23T22:06:26Z
2011-12-15T09:11:11Z
2002
 
Type Proceedings Paper
 
Identifier PROCEEDINGS OF THE ELEVENTH INTERNATIONAL WORKSHOP ON THE PHYSICS OF SEMICONDUCTOR DEVICES, VOL 1 & 2,4746,1316-1319
0-8194-4500-2
0277-786X
http://dspace.library.iitb.ac.in/xmlui/handle/10054/15250
http://hdl.handle.net/100/1909
 
Source 11th International Workshop on the Physics of Semiconductor Devices,New Delhi, INDIA,DEC 11-15, 2001
 
Language English