ICAR Research Data Repository for Knowledge Management
Channel engineering for sub-micron CMOS technologies
DSpace at IIT Bombay
View Archive Info| Field | Value | |
| Title |
Channel engineering for sub-micron CMOS technologies
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| Creator |
DIXIT, A
PAL, DK ROY, JN RAO, VR |
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| Subject |
mosfet
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| Description |
In this work, we have applied channel-engineering strategies for the Semiconductor Complex Limited (SCL) 0.8 mum CMOS process and studied the performance advantages using extensive 2-D device simulations. Our results clearly indicate that, with minimum adjustments to the process flow, one can achieve improved performance by appropriate choice of channel engineering techniques.
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| Publisher |
SPIE-INT SOC OPTICAL ENGINEERING
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| Date |
2011-10-23T22:12:33Z
2011-12-15T09:11:12Z 2011-10-23T22:12:33Z 2011-12-15T09:11:12Z 2002 |
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| Type |
Proceedings Paper
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| Identifier |
PROCEEDINGS OF THE ELEVENTH INTERNATIONAL WORKSHOP ON THE PHYSICS OF SEMICONDUCTOR DEVICES, VOL 1 & 2,4746,637-640
0-8194-4500-2 0277-786X http://dspace.library.iitb.ac.in/xmlui/handle/10054/15251 http://hdl.handle.net/100/1914 |
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| Source |
11th International Workshop on the Physics of Semiconductor Devices,New Delhi, INDIA,DEC 11-15, 2001
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| Language |
English
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