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Development of a multi-FPGA netlist partitioner and a general purpose graph partitioning system

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Title Development of a multi-FPGA netlist partitioner and a general purpose graph partitioning system
 
Creator GOWAIKAR, P
SOHONI, M
CHANDRAMOULI, M
PATKAR, S
 
Subject netlist partitioning
graphs
hypergraphs
eigenspectrum
submodular functions
 
Description We describe here a general purpose graph partitioning system, especially suitable for VLSI applications. The partitioner has at its core a spectral based graph partitioner. In our strategy, the input netlist is first coarsened into a smaller netlist and the core spectral partitioner then proceeds to partition this coarsened netlist. This coarse partition is then lifted to a partition of the original netlist. The coarsener is fairly subtle and uses the theory of submodular functions, and of matchings. We also highlight some of our results.
 
Publisher SPIE-INT SOC OPTICAL ENGINEERING
 
Date 2011-10-23T17:29:58Z
2011-12-15T09:11:15Z
2011-10-23T17:29:58Z
2011-12-15T09:11:15Z
1998
 
Type Proceedings Paper
 
Identifier PHOTOMASK AND X-RAY MASK TECHNOLOGY V,3412,252-260
0-8194-2864-7
0277-786X
http://dx.doi.org/10.1117/12.328816
http://dspace.library.iitb.ac.in/xmlui/handle/10054/15189
http://hdl.handle.net/100/1954
 
Source Conference on Photomask and X-Ray Mask Technology V,KAWASAKI, JAPAN,APR 09-10, 1998
 
Language English