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A comparative study of scaling properties of MOS transistors in CHE and CHISEL injection regime

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Title A comparative study of scaling properties of MOS transistors in CHE and CHISEL injection regime
 
Creator MOHAPATRA, NR
MAHAPATRA, S
RAO, VR
 
Description This paper analyzes in detail the correlation between gate and substrate currents in a deep sub-micron MOS transistor for different values of substrate voltage. The influence of channel length and oxide thickness on the gate injection and generation efficiency is studied from the point of non-volatile memories. The results show that the improvement of injection efficiency induced by the reverse substrate voltage becomes smaller as the gate length is reduced and also shows a turn around for smaller oxide thickness. The possible mechanisms responsible for such trends are discussed.
 
Publisher SPIE-INT SOC OPTICAL ENGINEERING
 
Date 2011-10-23T22:55:54Z
2011-12-15T09:11:17Z
2011-10-23T22:55:54Z
2011-12-15T09:11:17Z
2002
 
Type Proceedings Paper
 
Identifier PROCEEDINGS OF THE ELEVENTH INTERNATIONAL WORKSHOP ON THE PHYSICS OF SEMICONDUCTOR DEVICES, VOL 1 & 2,4746,686-689
0-8194-4500-2
0277-786X
http://dspace.library.iitb.ac.in/xmlui/handle/10054/15259
http://hdl.handle.net/100/1972
 
Source 11th International Workshop on the Physics of Semiconductor Devices,New Delhi, INDIA,DEC 11-15, 2001
 
Language English