Bottleneck identification techniques leading to simplified performance models for efficient design space exploration in VLSI memory systems
DSpace at IIT Bombay
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Title |
Bottleneck identification techniques leading to simplified performance models for efficient design space exploration in VLSI memory systems
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Creator |
HAZARI, G
DESAI, MP SRINIVAS, G |
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Subject |
architectures
technology |
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Description |
High performance VLSI systems are being built as multiprocessor systems-on-chip The number of processors and their performance is rising rapidly while the change is slower for the memories The memory system is often a performance bottleneck in terms of either its bandwidth or latency We propose sensitivity analysis as a means to pinpoint the bottleneck We Introduce a novel randomized technique to measure the sensitivities within cycle accurate simulators The sensitivity measures identify the bottleneck regions of the design space, within which simplified performance models can be used for optimization We demonstrate this methodology on the Augmint-MemSim simulator, which is a cycle accurate model for multi-processor systems with a distributed memory sub-system We empirically show that (i) Performance predictions from simplified models are strongly correlated with the simulator in the high sensitivity regions (u) The simplified models speed up design space exploration by 2 - 3 orders of magnitude over the simulator resulting in better design solutions
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Publisher |
IEEE COMPUTER SOC
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Date |
2011-10-25T04:50:10Z
2011-12-15T09:11:27Z 2011-10-25T04:50:10Z 2011-12-15T09:11:27Z 2010 |
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Type |
Proceedings Paper
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Identifier |
23RD INTERNATIONAL CONFERENCE ON VLSI DESIGN,15-20
978-1-4244-5541-6 http://dx.doi.org/10.1109/VLSI.Design.2010.45 http://dspace.library.iitb.ac.in/xmlui/handle/10054/15607 http://hdl.handle.net/100/2076 |
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Source |
23rd International Conference on VLSI Design/9th International Conference on Embedded Systems,Bangalore, INDIA,JAN 03-07, 2010
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Language |
English
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