Merge algorithms for intelligent vehicles
DSpace at IIT Bombay
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Title |
Merge algorithms for intelligent vehicles
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Creator |
RARAVI, G
SHINGDE, V RAMAMRITHAM, K BHARADIA, J |
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Subject |
automatic merge control
driving-time-to-intersection area-of-interest vehicle merge sequence vehicle interference continuous vehicle stream |
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Description |
There is an increased concern towards the design and development of computer-controlled automotive applications to improve safety, reduce accidents, increase traffic flow, and enhance comfort for drivers. Automakers are trying to make vehicles more intelligent by embedding processors which can be used to implement Electronic and Control Software (ECS) for taking smart decisions on the road or assisting the driver in doing the same. These ECS applications are high-integrity, distributed and real-time in nature. Inter-Vehicle Communication and Road-Vehicle Communication (IVC/RVC) mechanisms will only add to this intelligence by enabling distributed implementation of these applications. Our work studies one such application, namely Automatic Merge Control System, which ensures safe vehicle maneuver in the region where two roads intersect. We have discussed two approaches for designing this system both aimed at minimizing the Driving-Time-To-Intersection (DTTI) of vehicles, subject to certain constraints for ensuring safety. We have (i) formulated this system as an optimization problem which can be solved using standard solvers and (ii) proposed an intuitive approach namely, Head of Lane (HoL) algorithm which incurs less Computational overhead compared to optimization formulation. Simulations carried out using Matlab and C++ demonstrate that the proposed approaches ensure safe vehicle maneuvering at intersection regions. In this ongoing work, we are implementing the system on robotic vehicular platforms built in our lab.
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Publisher |
SPRINGER
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Date |
2011-10-24T08:43:48Z
2011-12-15T09:11:33Z 2011-10-24T08:43:48Z 2011-12-15T09:11:33Z 2007 |
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Type |
Proceedings Paper
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Identifier |
Next Generation Design and Verification Methodologies for Distributed Embedded Control Systems,51-65
978-1-4020-6253-7 http://dx.doi.org/10.1007/978-1-4020-6254-4_5 http://dspace.library.iitb.ac.in/xmlui/handle/10054/15367 http://hdl.handle.net/100/2134 |
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Source |
Workshop on Next Generation Design and Verification Methodologies for Distributed Embedded Control Systems,Bangalore, INDIA,JAN 05-06, 2007
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Language |
English
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