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FPGA implementation of a single-precision floating-point multiply-accumulator with single-cycle accumulation

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Title FPGA implementation of a single-precision floating-point multiply-accumulator with single-cycle accumulation
 
Creator PAIDIMARRI, A
CEVRERO, A
BRISK, P
IENNE, P
 
Description This paper describes an FPGA implementation of a single-precision floating-point multiply-accumulator (FPMAC) that supports single-cycle accumulation while maintaining high clock frequencies. A non-traditional internal representation reduces the cost of mantissa alignment within the accumulator. The FPMAC is evaluated on an Altera Stratix III FPGA.
 
Publisher IEEE COMPUTER SOC
 
Date 2011-10-24T12:20:24Z
2011-12-15T09:11:36Z
2011-10-24T12:20:24Z
2011-12-15T09:11:36Z
2009
 
Type Proceedings Paper
 
Identifier PROCEEDINGS OF THE 2009 17TH IEEE SYMPOSIUM ON FIELD PROGRAMMABLE CUSTOM COMPUTING MACHINES,267-270
978-0-7695-3716-0
http://dx.doi.org/10.1109/FCCM.2009.50
http://dspace.library.iitb.ac.in/xmlui/handle/10054/15417
http://hdl.handle.net/100/2176
 
Source 17th Annual IEEE Symposium on Field Programmable Custom Computing Machines,Napa, CA,APR 05-07, 2009
 
Language English