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Multiple fault testing of logic resources of SRAM-based FPGAs

DSpace at IIT Bombay

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Title Multiple fault testing of logic resources of SRAM-based FPGAs
 
Creator GOYAL, S
CHOUDHURY, M
RAO, SSSP
KUMAR, K
 
Description We shall present a simple but useful method which detects all multiple stuck-at faults in the application and configuration inputs of LUTs. A novel method for testing of stuck-at faults at control bits of flip flops has also been proposed. The aim is to integrate testing of LUTs, flip flops and multiplexers which will reduce the number of configurations and hence minimize the testing time.
 
Publisher IEEE COMPUTER SOC
 
Date 2011-10-24T17:58:41Z
2011-12-15T09:11:42Z
2011-10-24T17:58:41Z
2011-12-15T09:11:42Z
2005
 
Type Proceedings Paper
 
Identifier 18TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: POWER AWARE DESIGN OF VLSI SYSTEMS,742-747
0-7695-2264-5
1063-9667
http://dx.doi.org/10.1109/ICVD.2005.122
http://dspace.library.iitb.ac.in/xmlui/handle/10054/15488
http://hdl.handle.net/100/2232
 
Source 18th International Conference on VLSI Design/4th International Conference on Embedded Systems Design,Calcutta, INDIA,JAN 03-07, 2005
 
Language English