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An ultra low-energy DAC for successive approximation ADCs

DSpace at IIT Bombay

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Title An ultra low-energy DAC for successive approximation ADCs
 
Creator GOPAL, HV
BAGHINI, MS
 
Description An ultra low-energy successive approximation (SA) Analog-to-Digital Converter (ADC) is presented. The proposed ADC uses an energy-efficient unit capacitor array having a new switching arrangement in DAC for passive charge re-distribution. Reference levels are generated sequentially to get successive bits. The proposed method is analyzed theoretically and compared with other methods. Mathematical analysis shows that energy dissipation per bit can be reduced to the minimum possible normalized level, which is approximately 200 times lower than reported theoretical values. Simulation results of the proposed DAC in 90nm UMC MM CMOS process are also presented.
 
Publisher IEEE
 
Date 2011-10-25T08:52:39Z
2011-12-15T09:11:45Z
2011-10-25T08:52:39Z
2011-12-15T09:11:45Z
2010
 
Type Proceedings Paper
 
Identifier 2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS,3349-3352
978-1-4244-5309-2
0271-4302
http://dspace.library.iitb.ac.in/xmlui/handle/10054/15665
http://hdl.handle.net/100/2267
 
Source International Symposium on Circuits and Systems Nano-Bio Circuit Fabrics and Systems (ISCAS 2010),Paris, FRANCE,MAY 30-JUN 02, 2010
 
Language English