Response surface methodology for statistical characterization of nano CMOS devices and circuits
DSpace at IIT Bombay
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Title |
Response surface methodology for statistical characterization of nano CMOS devices and circuits
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Creator |
MANDE, S
CHANDORKAR, AN |
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Subject |
response surface
process variability response designs |
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Description |
The accurate prediction of the impact of process variations on circuit performance is very crucial in deciding the parametric yield of integrated circuits. This paper presents the simulation methodology for studying the impact of process variations on device and circuit performance in nanometer regime. In this paper, an empirical model for power and delay of 45nm node CMOS inverter is build using the well-known Response Surface Methodology. This work also compares the suitability of different response design in terms of model accuracy.
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Publisher |
IEEE
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Date |
2011-10-26T03:50:44Z
2011-12-15T09:11:48Z 2011-10-26T03:50:44Z 2011-12-15T09:11:48Z 2007 |
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Type |
Proceedings Paper
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Identifier |
PROCEEDINGS OF THE 2007 INTERNATIONAL WORKSHOP ON THE PHYSICS OF SEMICONDUCTOR DEVICES: IWPSD-2007,297-300
978-1-4244-1727-8 http://dspace.library.iitb.ac.in/xmlui/handle/10054/15901 http://hdl.handle.net/100/2296 |
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Source |
14th International Workshop on the Physics of Semiconductor Devices,Mumbai, INDIA,DEC 17-20, 2007
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Language |
English
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