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Reliability of single and dual layer Pt Nanocrystal devices for NAND flash applications : a 2-region model for endurance defect generation

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Title Reliability of single and dual layer Pt Nanocrystal devices for NAND flash applications : a 2-region model for endurance defect generation
 
Creator SINGH, PK
BISHT, G
SIVATHEJA, M
SANDHYA, C
MUKHOPADHYAY, G
MAHAPATRA, S
HOFMANN, R
SINGH, K
KRISHNA, N
 
Subject nonvolatile memory applications
performance
fabrication
metal nanocrystal
flash memory
mlc
reliability
 
Description Nanocrystal (NC) based memory devices are considered a possible alternative for floating gate (FG) replacement below 30nm node. In this work, endurance reliability of Pt NC devices is investigated for single layer (SL) and dual layer (DL) structures. The degradation in the devices due to Program/Erase (P/E) stress is investigated. Relative improvement in reliability of DL structure over SL structure is shown. A physical model for defect generation in the gate stack is proposed which is able to explain endurance and post-cycling characteristics. Dual layer structure is shown to have better inherent reliability over single layer structure.
 
Publisher IEEE
 
Date 2011-10-24T22:12:00Z
2011-12-15T09:11:48Z
2011-10-24T22:12:00Z
2011-12-15T09:11:48Z
2009
 
Type Proceedings Paper
 
Identifier 2009 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, VOLS 1 AND 2,301-306
978-1-4244-2888-5
http://dx.doi.org/10.1109/IRPS.2009.5173268
http://dspace.library.iitb.ac.in/xmlui/handle/10054/15531
http://hdl.handle.net/100/2303
 
Source 47th Annual IEEE International Reliability Physics Symposium,Montreal, CANADA,APR 26-30, 2009
 
Language English