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Parasitics effects in multi gate MOSFETs

DSpace at IIT Bombay

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Title Parasitics effects in multi gate MOSFETs
 
Creator MANOJ, CR
MANGAL, A
RAO, VR
TSUTSUI, K
IWAI, H
 
Description The parasitics in multi-gate transistors (MugFETs or FinFETs) are expected to significantly degrade the device and circuit performance in scaled technologies. Using extensive 3-D device and circuit simulations, the impact of parasitics on the device and circuit performance is systematically investigated. The results clearly identify the issues in integrating high-K gate dielectrics in scaled multi-gate transistors. We show from 3-D simulations that, when a high-K gate dielectric (with a K similar to 15, similar to hafnium oxide) is integrated in a multi-gate transistor a 5X increase (compared to the SiO(2)) in the off current occurs due to the fringing field induced barrier lowering effects. At the circuit level, our results show that, an order of magnitude degradation in the delay can take place, due to the unoptimized FinFET layouts.
 
Publisher IEEE
 
Date 2011-10-25T00:43:11Z
2011-12-15T09:11:50Z
2011-10-25T00:43:11Z
2011-12-15T09:11:50Z
2006
 
Type Proceedings Paper
 
Identifier 2006 INTERNATIONAL WORKSHOP ON NANO CMOS, PROCEEDINGS,255-260
978-1-4244-0603-6
http://dx.doi.org/10.1109/IWNC.2006.4570996
http://dspace.library.iitb.ac.in/xmlui/handle/10054/15558
http://hdl.handle.net/100/2324
 
Source International Workshop on Nano CMOS,Shizuoka, JAPAN,JAN 30-FEB 01, 2006
 
Language English