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Power reduction technique using multi-vt libraries

DSpace at IIT Bombay

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Title Power reduction technique using multi-vt libraries
 
Creator SRIVASTAV, M
RAO, SSSP
BHATNAGAR, H
 
Subject dsm
asic
leakage power
dft
high-vt
low-vt
 
Description In DSM technology leakage power dissipation in a cell becomes significant. Due to this significant rise in leakage power some measures should be taken quite early in the design flow to reduce it rather than realizing it later and either increasing the time to market by increasing the number of iterations or increasing the cost of production by using costly packaging. We have explored various ways of reducing leakage power in the design and recommended one, the Multi-Vt approach. We have carried out analysis using Multi-Vt approach over a test design on 130nm and 90nm technology. We have also highlighted on ways of how and where to apply this approach effectively in a typical ASIC design flow. We compare our results with all other approaches and demonstrate an average reduction in leakage power by almost 4.9 times compared to normal approaches without paying any penalty for speed or even area.
 
Publisher IEEE COMPUTER SOC
 
Date 2011-10-25T00:47:54Z
2011-12-15T09:11:50Z
2011-10-25T00:47:54Z
2011-12-15T09:11:50Z
2005
 
Type Proceedings Paper
 
Identifier FIFTH INTERNATIONAL WORKSHOP ON SYSTEM-ON-CHIP FOR REAL-TIME APPLICATIONS, PROCEEDINGS,363-367
0-7695-2403-6
http://dx.doi.org/10.1109/IWSOC.2005.92
http://dspace.library.iitb.ac.in/xmlui/handle/10054/15559
http://hdl.handle.net/100/2325
 
Source 5th International Workshop on System-on-Chip for Real-Time Applications,Banff, CANADA,JUL 20-24, 2005
 
Language English