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Benchmarking the device performance at SUB 22 NM node technologies using an SOC framework

DSpace at IIT Bombay

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Title Benchmarking the device performance at SUB 22 NM node technologies using an SOC framework
 
Creator SHRIVASTAVA, M
VERMA, B
BAGHINI, MS
RUSS, C
SHARMA, DK
GOSSNER, H
RAO, VR
 
Description For the first time this paper makes an attempt at predicting the System-on-Chip (SoC) performance (i.e. logic, SRAM, ESD and I/O) of various sub 20 nm channel length planar and non-planar SOI devices using extensive & well calibrated 3D device and mixed-mode TCAD simulations. It has been shown that the non-planar devices such as FinFETs are not the ideal choice for SoC applications and perform poorly in comparison to the Ultra thin body (UTB) planar SOT MOSFETs. We further show different strategies to optimize the planar UTB MOSFETs for improved ESD robustness and I/O performance.
 
Publisher IEEE
 
Date 2011-10-25T15:59:18Z
2011-12-15T09:12:00Z
2011-10-25T15:59:18Z
2011-12-15T09:12:00Z
2009
 
Type Proceedings Paper
 
Identifier 2009 IEEE INTERNATIONAL ELECTRON DEVICES MEETING,471-474
978-1-4244-5639-0
http://dspace.library.iitb.ac.in/xmlui/handle/10054/15761
http://hdl.handle.net/100/2419
 
Source IEEE International Electron Devices Meeting (IEDM 2009),Baltimore, MD,DEC 07-09, 2009
 
Language English