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A pipe lined simulation approach for logic emulation using multi-FPGA platforms

DSpace at IIT Bombay

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Title A pipe lined simulation approach for logic emulation using multi-FPGA platforms
 
Creator BAVISKAR, D
PATKAR, S
 
Description Emulation of a large system on a multi-FPGA platform not only involves partitioning the system into multiple modules subject to given capacity and resource constraints, but also involves achieving higher throughput, lower cost of emulation and less communication overhead. Many good scheduling algorithms have been reported, however due to the lack of pipelining they fail to achieve high system throughput. An intelligent hardware scheduling approach is essential for obtaining high system throughput with possibly lower overheads. In this paper, we propose a scalable, high performance, low cost approach for simulation of multi-FPGA systems. We convert the unbalanced partitioned system into a balanced pipeline and maximize the throughput of the system. Our experiments on reference designs have shown a speed-up of up to 8.57 x with a 10% hardware overhead over the conventional simulation approaches.
 
Publisher IEEE
 
Date 2011-10-25T18:56:20Z
2011-12-15T09:12:05Z
2011-10-25T18:56:20Z
2011-12-15T09:12:05Z
2009
 
Type Proceedings Paper
 
Identifier ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5,1141-1144
978-1-4244-3827-3
http://dspace.library.iitb.ac.in/xmlui/handle/10054/15794
http://hdl.handle.net/100/2459
 
Source IEEE International Symposium on Circuits and Systems (ISCAS 2009),Taipei, TAIWAN,MAY 24-27, 2009
 
Language English