ICAR Research Data Repository for Knowledge Management
Optimization of hetero junction n-channel tunnel FET with high-k spacers
DSpace at IIT Bombay
View Archive Info| Field | Value | |
| Title |
Optimization of hetero junction n-channel tunnel FET with high-k spacers
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| Creator |
VIRANI, HG
KOTTANTHARAYIL, A |
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| Subject |
field-effect transistor
kappa gate dielectrics strained silicon device design |
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| Description |
Use of high-k spacers to boost the ON state current of SiGe-Si hetero junction tunnel FETs is proposed for the first time. Extensive device simulations have been conducted to understand the device physics. It is shown that the fringing fields through the spacer enhances the ON state current without modifying the OFF state current or the subthreshold swing. The spacer k can be traded off against the Ge mole fraction in SiGe. It is shown that the OFF state current can be further reduced by employing a drain side overlap in combination with the high-k spacer. Device designs that satisfy the ITRS requirements for 20nm gate length technology for HP, LOP and LSTP applications are proposed using Ge mole fraction of 0.4 to 0.48 in SiGe and spacer k of 14, which can be integrated with presently available technologies.
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| Publisher |
IEEE
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| Date |
2011-10-25T19:30:44Z
2011-12-15T09:12:06Z 2011-10-25T19:30:44Z 2011-12-15T09:12:06Z 2009 |
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| Type |
Proceedings Paper
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| Identifier |
2009 2ND INTERNATIONAL WORKSHOP ON ELECTRON DEVICES AND SEMICONDUCTOR TECHNOLOGY,76-81
978-1-4244-3831-0 http://dspace.library.iitb.ac.in/xmlui/handle/10054/15801 http://hdl.handle.net/100/2467 |
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| Source |
2nd International Workshop on Electron Devices and Semiconductor Technology,Bombay, INDIA,JUN 01-02, 2009
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| Language |
English
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