Recent advances in charge trap flash memories
DSpace at IIT Bombay
View Archive InfoField | Value | |
Title |
Recent advances in charge trap flash memories
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Creator |
SANDHYA, C
SINGH, PK GUPTA, S ROHRA, H SHIVATHEJA, M GANGULY, U HOFMANN, R MUKHOPADHYAY, G MAHAPATRA, S VASI, J |
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Subject |
metal nanocrystal memories
performance fabrication device program/erase reliability retention operation charge trap flash sonos nanocrystal |
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Description |
This paper reviews recent advances in Charge Trap Flash (CTF) memories. CTFs are predicted to replace the traditional floating-gate flash devices beyond the 32 nm node. The paper focuses on work done at IIT Bombay in the areas of both nitride-based SONOS devices as well as nanocrystal (NC)-based devices. For SONOS devices, results are presented for optimization of the nitride layer to obtain the best characteristics, and the simulation of the program/erase transients. For NC devices, experimental characteristics of single and dual layer cells, as well as simulation results are presented.
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Publisher |
IEEE
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Date |
2011-10-25T20:31:44Z
2011-12-15T09:12:07Z 2011-10-25T20:31:44Z 2011-12-15T09:12:07Z 2009 |
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Type |
Proceedings Paper
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Identifier |
2009 2ND INTERNATIONAL WORKSHOP ON ELECTRON DEVICES AND SEMICONDUCTOR TECHNOLOGY,192-196
978-1-4244-3831-0 http://dspace.library.iitb.ac.in/xmlui/handle/10054/15813 http://hdl.handle.net/100/2480 |
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Source |
2nd International Workshop on Electron Devices and Semiconductor Technology,Bombay, INDIA,JUN 01-02, 2009
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Language |
English
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