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Sub-20 nm gate length FinFET design : can High-kappa spacers make a difference?

DSpace at IIT Bombay

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Title Sub-20 nm gate length FinFET design : can High-kappa spacers make a difference?
 
Creator SACHID, AB
FRANCIS, R
BAGHINI, MS
SHARMA, DK
BACH, KH
MAHNKOPF, R
RAO, VR
 
Subject devices
 
Description Sub-20 nm gate length FinFETs, are constrained by the very thin fin thickness (T(FIN)) necessary to maintain acceptable short-channel performance. For the 45 nm technology node and below, a novel device design methodology for undoped underlapped FinFETs with high-kappa spacers is presented to achieve higher circuit speed and SRAM cells with higher stability, lower leakage, faster access times and higher robustness to process variations compared to overlapped FinFETs. While comparing different FinFETs, we propose ON-current per fin as the parameter to be optimized instead of ON-current normalized to electrical width.
 
Publisher IEEE
 
Date 2011-10-25T21:52:52Z
2011-12-15T09:12:09Z
2011-10-25T21:52:52Z
2011-12-15T09:12:09Z
2008
 
Type Proceedings Paper
 
Identifier IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2008, TECHNICAL DIGEST,697-700
978-1-4244-2377-4
http://dspace.library.iitb.ac.in/xmlui/handle/10054/15829
http://hdl.handle.net/100/2500
 
Source IEEE International Electron Devices Meeting,San Francisco, CA,DEC 15-17, 2008
 
Language English