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Circuit performance improvement using PDSOI-DTMOS devices with a novel optimal sizing scheme considering body parasitics

DSpace at IIT Bombay

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Title Circuit performance improvement using PDSOI-DTMOS devices with a novel optimal sizing scheme considering body parasitics
 
Creator ANAND, B
RAO, VR
DESAI, MP
 
Description In sub-1V CNIOS technologies, the approach of increasing speed and reducing area of circuits with scaling is facing a severe challenge due to exponential increase in leakage currents. The DTMOS device has an ideal subthreshold slope and can be realized in mainstream CNIOS technologies that provide device isolation. PDSOI technology offers the desirable isolation of device bodies. However, the resistance and capacitance of body degrade the performance of PDSOI-DTMOS circuits. In order to maximize the performance of PDSOT-DTMOS circuits, we propose simple but accurate delay and input capacitance models and layout guidelines for DTMOS logic gates, which incorporate the effect of the body parasitics. We then use these models to optimize the sizing of PDSOI-DTMOS devices to maximize circuit performance. With this approach, we observe that DTNIOS offers a 60% reduction in leakage power for a given circuit speed in 50nm technology.
 
Publisher IEEE
 
Date 2011-10-26T08:15:15Z
2011-12-15T09:12:10Z
2011-10-26T08:15:15Z
2011-12-15T09:12:10Z
2007
 
Type Proceedings Paper
 
Identifier 2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Proceedings of Technical Papers,240-243
978-1-4244-0582-4
http://dspace.library.iitb.ac.in/xmlui/handle/10054/15952
http://hdl.handle.net/100/2506
 
Source International Symposium on VLSI Design, Automation and Test,Hsinchu, TAIWAN,APR 25-27, 2007
 
Language English