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The impact of gate dielectric nitridation methodology on NBTI of SiON p-MOSFETs as studied by UF-OTF technique
DSpace at IIT Bombay
View Archive Info| Field | Value | |
| Title |
The impact of gate dielectric nitridation methodology on NBTI of SiON p-MOSFETs as studied by UF-OTF technique
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| Creator |
MAHETA, VD
OLSEN, C AHMED, K MAHAPATRA, S |
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| Subject |
bias temperature instability
trap generation interface |
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| Description |
The impact of gate dielectric nitridation methodology on time, temperature and field dependence of NBTI in SiON pMOSFETs is studied using Ultra-Fast On-The-Fly I(DLIN) technique with 1 mu s resolution. It is shown that PNO devices with proper PNA show lower degradation magnitude, higher field dependence and therefore higher safe operating voltage compared to RTNO and PNO devices with improper PNA despite atomic N% is higher in PNO devices with proper PNA.
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| Publisher |
IEEE
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| Date |
2011-10-25T23:37:55Z
2011-12-15T09:12:13Z 2011-10-25T23:37:55Z 2011-12-15T09:12:13Z 2008 |
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| Type |
Proceedings Paper
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| Identifier |
IPFA 2008: PROCEEDINGS OF THE 15TH INTERNATIONAL SYMPOSIUM ON THE PHYSICAL & FAILURE ANALYSIS OF INTEGRATED CIRCUITS,255-259
978-1-4244-2039-1 http://dspace.library.iitb.ac.in/xmlui/handle/10054/15848 http://hdl.handle.net/100/2536 |
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| Source |
15th International Symposium on the Physical and Failure Analysis of Integrated Circuits,Singapore, SINGAPORE,JUL 07-11, 2008
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| Language |
English
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