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Efficient translation of Statecharts to hardware circuits

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Title Efficient translation of Statecharts to hardware circuits
 
Creator RAMESH, S
 
Description Traditional description techniques like Finite State Machines (FSMs) are inadequate for current day complex hardware control circuits as they are flat and unstructured Recently Harel defined Statecharts by introducing concurrent and hierarchical structure to FSMs. Statecharts can be implemented in hardware using the conventional implementation scheme of combinational-logic block with a feed-back register The main problem here is the encoding of state configurations. The encoding, besides uniquely identifying configurations should be easily decomposable into the codes of constituent states so that the set of permissible transitions in these states can be performed and the resulting outputs and the next configuration can be computed This paper proposes a new scheme for encoding statechart configurations. The distinguishing feature of this scheme is to encode not only basic states but also intermediate states. The encoding is based upon the hierarchical and concurrent structure of statecharts. It has been shown both theoretically and experimentally that the scheme performs better than existing encoding schemes.
 
Publisher IEEE COMPUTER SOC
 
Date 2011-10-27T07:40:10Z
2011-12-15T09:12:18Z
2011-10-27T07:40:10Z
2011-12-15T09:12:18Z
1999
 
Type Proceedings Paper
 
Identifier TWELFTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS,384-389
0-7695-0013-7
http://dspace.library.iitb.ac.in/xmlui/handle/10054/16224
http://hdl.handle.net/100/2589
 
Source 12th International Conference on VLSI Design,GOA, INDIA,JAN 07-10, 1999
 
Language English