ICAR Research Data Repository for Knowledge Management
A novel low power multilevel current mode interconnect system
DSpace at IIT Bombay
View Archive Info| Field | Value | |
| Title |
A novel low power multilevel current mode interconnect system
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| Creator |
JOSHI, S
SHARMA, D |
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| Subject |
readout circuit
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| Description |
We propose circuits for low power high throughput multilevel current mode signaling using 2 bit simultaneous data transfer A novel design of the receiver for very low line voltage swings is discussed. The technique involves matching the receiver impedance to the line impedance thereby reducing the ringing on the wire. Simulation results show upto 50% reduction in latency and upto 100 times reduction in power over voltage mode buffer insertion techniques. We also show that the delays through this system are largely independent of the interconnect lengths. Data rates of upto 1Gb/s have been obtained. A power consumption model is derived for the system which matches the simulation results to within 5%.
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| Publisher |
IEEE COMPUTER SOC
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| Date |
2011-10-26T13:22:30Z
2011-12-15T09:12:21Z 2011-10-26T13:22:30Z 2011-12-15T09:12:21Z 2006 |
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| Type |
Proceedings Paper
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| Identifier |
IEEE Computer Society Annual Symposium on VLSI, Proceedings: EMERGING VLSI TECHNOLOGIES AND ARCHITECTURES,122-127
0-7695-2533-4 http://dspace.library.iitb.ac.in/xmlui/handle/10054/16021 http://hdl.handle.net/100/2616 |
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| Source |
IEEE-Computer-Society Annual Symposium on VLSI,Karlsruhe, GERMANY,MAR 02-03, 2006
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| Language |
English
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