Record Details


Field	Value

Title	Synchronous protocol automata : a framework for. modelling and verification of SoC communication architectures

Creator	D'SILVA, V RAMESH, S SOWMYA, A

Description	Plug-n-Play style Intellectual Property(IP) reuse in System on Chip(SoC) design is facilitated by the use of an on-chip bus architecture. We present a synchronous, Finite State Machine based framework for modelling communication aspects of such architectures. This formalism has been developed via interaction with designers and the industry and is intuitive and lightweight. We have developed cycle accurate methods to formally specify protocol compatibility and component composition and show how our model can be used for compatibility verification, interface synthesis and model checking with automated specification. We demonstrate the utility of our framework by modelling the AMBA bus architecture including details such as pipelined operation, burst and split transfers, the AHB-APB bridge and arbitration features.

Publisher	IEEE COMPUTER SOC

Date	2011-10-26T17:18:14Z 2011-12-15T09:12:26Z 2011-10-26T17:18:14Z 2011-12-15T09:12:26Z 2004

Type	Proceedings Paper

Identifier	DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS,390-395 0-7695-2085-5 http://dspace.library.iitb.ac.in/xmlui/handle/10054/16071 http://hdl.handle.net/100/2661

Source	Design, Automation and Test in Europe Conference and Exhibition (DATE 04),Paris, FRANCE,FEB 16-20, 2004

Language	English

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