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FPGA implementation of median filter

DSpace at IIT Bombay

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Title FPGA implementation of median filter
 
Creator MAHESHWARI, R
RAO, SSSP
POONACHA, PG
 
Description This paper gives the algorithm and implementation details of a sliding real time 3 x 3 median filter. The design is implemented on a Xilinx XC4010 FPGA chip. It is tested and integrated at ER&DC1, Trivandrum. The design is tailored to exploit certain features of sliding windows. The Algorithm used to implement median filter is very efficient and implementation results show the significant improvements in operating frequency and hardware requirements over general purpose techniques.
 
Publisher I E E E, COMPUTER SOC PRESS
 
Date 2011-10-27T11:20:44Z
2011-12-15T09:12:35Z
2011-10-27T11:20:44Z
2011-12-15T09:12:35Z
1997
 
Type Proceedings Paper
 
Identifier TENTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS,523-524
0-8186-7755-4
http://dspace.library.iitb.ac.in/xmlui/handle/10054/16280
http://hdl.handle.net/100/2759
 
Source 10th International Conference on VLSI Design,HYDERABAD, INDIA,JAN 04-07, 1997
 
Language English