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VLSI implementation of artificial neural network based digital multiplier and adder
DSpace at IIT Bombay
View Archive Info| Field | Value | |
| Title |
VLSI implementation of artificial neural network based digital multiplier and adder
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| Creator |
RANADE, R
BHANDARI, S CHANDORKAR, AN |
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| Publisher |
I E E E, COMPUTER SOC PRESS
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| Date |
2011-10-27T15:31:20Z
2011-12-15T09:12:42Z 2011-10-27T15:31:20Z 2011-12-15T09:12:42Z 1995 |
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| Type |
Proceedings Paper
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| Identifier |
NINTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS,318-319
0-8186-7228-5 http://dspace.library.iitb.ac.in/xmlui/handle/10054/16340 http://hdl.handle.net/100/2840 |
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| Source |
9th International Conference on VLSI Design - VLSI in Mobile Communication (VLSI Design 96),BANGALORE, INDIA,JAN 03-06, 1996
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| Language |
English
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