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On buffering schemes for long multi-layer nets

DSpace at IIT Bombay

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Title On buffering schemes for long multi-layer nets
 
Creator PRASAD, V
DESAI, MP
 
Subject vlsi
buffer circuit
circuit optimisation
delays
 
Description We consider the problem of minimizing the delay in signal transmission over point-to-point connections across multiple metal layers in a VLSI circuit. We present an exact solution for the two layer case. This exact solution, however, is irregular and dependent on the length of the net. We look for approximate solutions which are not only regular but are independent of the length of the net. We show that two of these approximate solutions yield delays that are within a constant of the optimal solution. We have seen that our results hold true even for the three-layer case. We conjecture that our models can be inductively extended for multi-layer nets as well.
 
Publisher IEEE
 
Date 2008-12-20T05:46:55Z
2011-11-27T21:05:53Z
2011-12-15T09:56:20Z
2008-12-20T05:46:55Z
2011-11-27T21:05:53Z
2011-12-15T09:56:20Z
2004
 
Type Article
 
Identifier Proceedings of the 17th International Conference on VLSI Design, Mumbai, India, 5-9 January 2004, 455-460
0-7695-2072-3
10.1109/ICVD.2004.1260964
http://hdl.handle.net/10054/423
http://dspace.library.iitb.ac.in/xmlui/handle/10054/423
 
Language en