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Variance reduction in Monte Carlo capacitance extraction

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Field Value
 
Title Variance reduction in Monte Carlo capacitance extraction
 
Creator BATTERYWALA, SH
DESAI, MP
 
Subject monte carlo methods
capacitance
error analysis
statistical methods
 
Description In this article we address efficiency issues in implementation of Monte Carlo algorithm For 3D capacitance extraction. Error bounds in statistical capacitance estimation are discussed. Methods to tighten them through variance reduction techniques are detailed. Sample values in implementation of Monte Carlo algorithm are completely determined by the first hop in random walk. This in turn facilitates application of variance reduction techniques like importance sampling and stratified sampling to be used effectively. Experimental results indicate average speedup of 16X in simple uniform dielectric technologies, 7.3X in technologies with layers of dielectrics and 4.6X in technologies having conformal dielectrics.
 
Publisher IEEE
 
Date 2008-12-20T05:47:53Z
2011-11-28T00:12:18Z
2011-12-15T09:56:25Z
2008-12-20T05:47:53Z
2011-11-28T00:12:18Z
2011-12-15T09:56:25Z
2005
 
Type Article
 
Identifier Proceedings of the 18th International Conference on VLSI Design, Kolkata, India, 3-7 January 2005, 85-90
0-7695-2264-5
10.1109/ICVD.2005.169
http://hdl.handle.net/10054/424
http://dspace.library.iitb.ac.in/xmlui/handle/10054/424
 
Language en