Record Details

Interface design for rationally clocked GALS systems

DSpace at IIT Bombay

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Field Value
 
Title Interface design for rationally clocked GALS systems
 
Creator MEKIE, JOYCEE
CHAKRABORTY, SUPRATIK
VENKATARAMANI, G
THIAGARAJAN, PS
SHARMA, DK
 
Subject asynchronous circuit
logic design
 
Description We investigate the problem of designing interface circuits for rationally clocked modules in GALS systems. As a key contribution, we show that knowledge of flow-control protocols can be used to significantly optimize synchronization mechanisms. We present delay-augmented netcharts as a formalism for representing communication protocols and describe techniques to analyze them. We use the results of our analysis to design a simple yet generic interface that is optimized for the given protocol and is free from synchronization failures. We show by means of case studies the inherent advantages of our methodology over an existing solution technique.
 
Publisher IEEE
 
Date 2008-12-15T10:37:36Z
2011-11-27T12:03:26Z
2011-12-15T09:56:30Z
2008-12-15T10:37:36Z
2011-11-27T12:03:26Z
2011-12-15T09:56:30Z
2006
 
Type Article
 
Identifier Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems, Grenoble, France, 13-15 March 2006, 1-12
0-7695-2498-2
10.1109/ASYNC.2006.19
http://hdl.handle.net/10054/323
http://dspace.library.iitb.ac.in/xmlui/handle/10054/323
 
Language en