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Interconnect delay minimization using a novel pre-mid-post buffer strategy

DSpace at IIT Bombay

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Title Interconnect delay minimization using a novel pre-mid-post buffer strategy
 
Creator PRASAD, V
DESAI, MP
 
Subject buffer circuit
circuit optimisation
integrated circuit design
integrated circuit modelling
 
Description We consider the problem of minimizing the delay in transporting a signal across a distance in a VLSI circuit. The problem can be restated as a combined buffer insertion, buffer sizing and wire sizing problem. We propose a simple buffering architecture for this problem and show that this architecture achieves a near optimal solution. We also derive simple models for a buffered wire which are suitable for high level design.
 
Publisher IEEE
 
Date 2008-12-19T09:54:25Z
2011-11-27T14:58:56Z
2011-12-15T09:56:33Z
2008-12-19T09:54:25Z
2011-11-27T14:58:56Z
2011-12-15T09:56:33Z
2003
 
Type Article
 
Identifier Proceedings of the 16th International Conference on VLSI Design, New Delhi, India, 4-8 January 2003, 417-422
0-7695-1868-0
10.1109/ICVD.2003.1183171
http://hdl.handle.net/10054/393
http://dspace.library.iitb.ac.in/xmlui/handle/10054/393
 
Language en