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Detailed analysis of FIBL in MOS transistors with high-k gate dielectrics

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Title Detailed analysis of FIBL in MOS transistors with high-k gate dielectrics
 
Creator MOHAPATRA, NR
DESAI, MP
RAMGOPAL RAO, V
 
Subject mosfet
dielectric thin films
permittivity
semiconductor device models
 
Description This paper analyzes in detail the fringing induced barrier lowering (FIBL) in MOS transistors with high-k gate dielectrics using 2D device simulations. We found that the device short channel performance is degraded with increase in gate dielectric permittivity (K/sub gate/) due to an increase in the dielectric physical thickness to channel length ratio. For K/sub gate/ greater than K/sub si/, we observe a substantial coupling between source and drain regions through the gate insulator. This fact is validated by extensive device simulations with different channel length and overlap length over a wide range of dielectric permittivities. We also observe that the overlap length is an important parameter for optimizing DC performance in short channel MOS transistors. The effect of stacked gate dielectric and lateral channel engineering on the performance of high-k gate dielectric MOS transistors is also studied to substantiate the above observations.
 
Publisher IEEE
 
Date 2008-12-19T10:48:27Z
2011-11-27T18:57:16Z
2011-12-15T09:56:35Z
2008-12-19T10:48:27Z
2011-11-27T18:57:16Z
2011-12-15T09:56:35Z
2003
 
Type Article
 
Identifier Proceedings of the 16th International Conference on VLSI Design, New Delhi, India, 4-8 January 2003, 99-104
0-7695-1868-0
10.1109/ICVD.2003.1183121
http://hdl.handle.net/10054/400
http://dspace.library.iitb.ac.in/xmlui/handle/10054/400
 
Language en