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Nitride engineering and the effect of interfaces on charge trap flash performance and reliability

DSpace at IIT Bombay

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Title Nitride engineering and the effect of interfaces on charge trap flash performance and reliability
 
Creator SANDHYA, C
GANGULY, U
SINGH, KK
SINGH, PK
OLSEN, C
SEUTTER, SM
HUNG, R
CONTI, G
AHMED, K
KRISHNA, N
VASI, J
MAHAPATRA, S
 
Subject mis devices
flash memories
integrated circuit reliability
integrated memory circuits
silicon compounds
 
Description The performance and reliability of charge trap flash with single and bi-layer Si-rich and N-rich nitride as the storage node is studied. Single layer devices show lower memory window and poor cycling endurance, and the underlying physical mechanisms for these issues are explained. An engineered trap layer consisting of Si-rich and N-rich nitride interfaced by a SiON barrier layer is proposed. The effect of varying the SiON interfacial layer position on memory window and reliability is investigated. Optimum bi-layer device shows higher memory window and negligible degradation due to cycling (at higher memory window) compared to single layer films. The role of SiON interface in improving the performance and reliability of bi-layer stacks is explained.
 
Publisher IEEE
 
Date 2008-12-15T10:39:57Z
2011-11-27T13:28:49Z
2011-12-15T09:56:44Z
2008-12-15T10:39:57Z
2011-11-27T13:28:49Z
2011-12-15T09:56:44Z
2008
 
Type Article
 
Identifier Proceedings of the IEEE International Reliability Physics Symposium, Phoenix, USA, 27 April-1 May 2008, 406-411.
978-1-4244-2049-0
10.1109/RELPHY.2008.4558919
http://hdl.handle.net/10054/328
http://dspace.library.iitb.ac.in/xmlui/handle/10054/328
 
Language en