A predictive reliability model for PMOS bias temperature degradation
DSpace at IIT Bombay
View Archive InfoField | Value | |
Title |
A predictive reliability model for PMOS bias temperature degradation
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Creator |
MAHAPATRA, S
ALAM, MA |
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Subject |
mosfet
semiconductor device models semiconductor device reliability |
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Description |
Bias temperature degradation is studied in p-MOSFETs. The physical mechanisms responsible for degradation over a wide range of stress bias and temperature have been identified. A novel scaling methodology is proposed that helps in obtaining a simple, analytical model useful for reliability projection.
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Publisher |
IEEE
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Date |
2008-12-10T04:58:00Z
2011-11-28T07:13:29Z 2011-12-15T09:56:55Z 2008-12-10T04:58:00Z 2011-11-28T07:13:29Z 2011-12-15T09:56:55Z 2002 |
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Type |
Article
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Identifier |
Proceedings of the International Electron Devices Meeting, San Francisco CA, USA, 8-11 December 2002, 505-508
0-7803-7462-2 10.1109/IEDM.2002.1175890 http://hdl.handle.net/10054/245 http://dspace.library.iitb.ac.in/xmlui/handle/10054/245 |
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Language |
en
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