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Estimation of process variation impact on DG-FinFET device performance using Plackett-Burman design of experiment method

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Title Estimation of process variation impact on DG-FinFET device performance using Plackett-Burman design of experiment method
 
Creator CHANDORKAR, AN
MANDE, SUDHAKAR
IWAI, HIROSHI
 
Subject design of experiments
field effect transistors
gates (transistor)
integrated circuits
 
Description This paper studies various Double-Gate (DG) FinFET structures optimized for better “off state” and “on state” performance. In this work, we study the impact of process variation on the performance of DG-FinFET device with 20nm gate length. This was achieved through calibrated TCAD simulations. We show that the spacer thickness variation has the highest impact on Ion of the DG-FinFETs. In this work, we also have demonstrated the suitability of method of Plackett-Burman Design of Experiments (PB-DOE), for accurate estimation of the impact of the large number of process parameter-variations on DG-FinFET device’s electrical performance.
 
Publisher IEEE
 
Date 2009-01-29T12:10:55Z
2011-11-28T07:20:30Z
2011-12-15T09:56:55Z
2009-01-29T12:10:55Z
2011-11-28T07:20:30Z
2011-12-15T09:56:55Z
2008
 
Type Article
 
Identifier Proceedings of the 9th International Conference on Solid-State and Integrated-Circuit Technology, Beijing, China, 20-23 Octomber 2008, 215-218
978-1-4244-2185-5
10.1109/ICSICT.2008.4734510
http://hdl.handle.net/10054/593
http://dspace.library.iitb.ac.in/xmlui/handle/10054/593
 
Language en