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Performance of channel engineered SDODEL MOSFET for mixed signal applications

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Title Performance of channel engineered SDODEL MOSFET for mixed signal applications
 
Creator SARKAR, P
MALLIK, A
SARKAR, CK
RAMGOPAL RAO, V
 
Subject computer simulation
signal analysis
drain current
capacitance
 
Description In this paper, with the help of simulations the concepts of source/drain (S/D) impurity profile engineering are proposed for reduction of the junction capacitance (Cj). It has been recently shown that it is possible to realize the benefits of PD- SOI technologies with the help of Source/Drain On Depletion Layer (SDODEL) MOSFETs, employing the bulk technologies. Here, for the first time, we investigated analog performance improvement with Single Halo SDODEL MOSFETs, as well as Double Halo SDODEL MOSFET and compared their performances with Double Halo MOSFETs (which will henceforth be referred as Control MOSFETs) with extensive process and device simulations. Our results show that, in Single Halo SDODEL MOSFET there is a significant improvement in the intrinsic device performance for analog applications (such as device gain, gm/IDetc.) for sub 100nm technologies.
 
Publisher IEEE
 
Date 2009-01-22T05:58:21Z
2011-11-28T07:15:59Z
2011-12-15T09:56:57Z
2009-01-22T05:58:21Z
2011-11-28T07:15:59Z
2011-12-15T09:56:57Z
2005
 
Type Article
 
Identifier Proceedings of the IEEE Conference on Electron Devices and Solid-State Circuits, Hong Kong, 19-21 December 2005, 687-690
0-7803-9339-2
10.1109/EDSSC.2005.1635368
http://hdl.handle.net/10054/581
http://dspace.library.iitb.ac.in/xmlui/handle/10054/581
 
Language en