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The effect of CHE and CHISEL programming operation on drain disturb in flash EEPROMs

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Title The effect of CHE and CHISEL programming operation on drain disturb in flash EEPROMs
 
Creator NAIR, DR
MOHAPATRA, NR
MAHAPATRA, S
SHUKURI, S
BUDE, JD
 
Subject flash memories
hot carriers
integrated circuit testing
integrated memory circuits
tunnelling
 
Description In this paper, we report an extensive study of drain disturb in isolated cells under channel hot electron (CHE) and channel initiated secondary electron (CHISEL) has been identified to be initiated by band-to-band (BB) tunnelling as opposed to S/D leakage for CHE operation. This is verified by measurements under different temperature and on cells having different floating gate length (Lfg). The effect of program/erase (P/E) cycling on drain distrubs is explored for different control gate bias (Vcg) and Vd. After cycling the program/disturb margin has been found to decrease for the charge gain mode, while it remains constant for the charge loss mode. The program/disturb margin for CHISEL operation is slightly lower compared to CHE operation under identical (initial) programming time (Tp). However the margin becomes identical when compared after 100K P/E cycling.
 
Publisher IEEE
 
Date 2008-12-11T06:00:18Z
2011-11-27T14:18:48Z
2011-12-15T09:57:05Z
2008-12-11T06:00:18Z
2011-11-27T14:18:48Z
2011-12-15T09:57:05Z
2003
 
Type Article
 
Identifier Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits, Singapore, 7-11 July 2003, 164-167
0-7803-7722-2
http://hdl.handle.net/10054/289
http://dspace.library.iitb.ac.in/xmlui/handle/10054/289
 
Language en