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An algorithm for minimising the number of test cycles

DSpace at IIT Bombay

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Field Value
 
Title An algorithm for minimising the number of test cycles
 
Creator DIWAN, AJIT A
 
Subject vlsi
fault location
integrated circuit testing
production testing
shift registers
 
Description The scan-path method for testing a VLSI circuit uses a shift register to store the test vectors, and a sequence of test patterns is applied by shifting in new patterns one bit at a time. In this paper present an algorithm to find the order in which the test patterns should be applied in order to minimise the number of shift operations required. The algorithm can be shown to be optimal under certain conditions.
 
Publisher IEEE
 
Date 2009-05-14T13:43:51Z
2011-11-28T08:01:38Z
2011-12-15T09:57:24Z
2009-05-14T13:43:51Z
2011-11-28T08:01:38Z
2011-12-15T09:57:24Z
1991
 
Type Article
 
Identifier Proceedings of the 4th CSI/IEEE International Symposium on VLSI Design, New Delhi, India, 4-8 January 1991, 154-156
0-8186-2125-7
10.1109/ISVD.1991.185109
http://hdl.handle.net/10054/1363
http://dspace.library.iitb.ac.in/xmlui/handle/10054/1363
 
Language en