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The impact of channel engineering on the performance reliability and scaling of CHISEL NOR flash EEPROMs

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Field Value
 
Title The impact of channel engineering on the performance reliability and scaling of CHISEL NOR flash EEPROMs
 
Creator MOHAPATRA, NR
NAIR, DR
MAHAPATRA, S
RAMGOPAL RAO, V
SHUKURI, S
 
Subject nor circuits
flash memories
integrated circuit reliability
 
Description The programming performance, cycling endurance and scaling of CHISEL NOR flash EEPROMs is studied for two different (halo and no-halo) channel engineering schemes. Programming speed under identical bias, bias requirements under similar programming time, cycling endurance and drain disturb are compared. The scaling properties of programming time (at a fixed bias), bias (at a fixed programming time) and program/disturb margin are studied as cell floating gate length is scaled. The relative merits of these channel engineering schemes are discussed from the viewpoint of futuristic CHISEL cell design.
 
Publisher IEEE
 
Date 2008-12-11T06:02:38Z
2011-11-28T08:03:38Z
2011-12-15T09:57:25Z
2008-12-11T06:02:38Z
2011-11-28T08:03:38Z
2011-12-15T09:57:25Z
2003
 
Type Article
 
Identifier Proceedings of the 33rd Conference on European Solid-State Device Research, Estoril, Portugal, 16-18 September 2003, 541-544
0-7803-7999-3
10.1109/ESSDERC.2003.1256933
http://hdl.handle.net/10054/294
http://dspace.library.iitb.ac.in/xmlui/handle/10054/294
 
Language en