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Layout-driven timing optimization by Generalized De Morgan transform

DSpace at IIT Bombay

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Title Layout-driven timing optimization by Generalized De Morgan transform
 
Creator CHAKRABORTY, SUPRATIK
MURGAI, RAJEEV
 
Subject circuit layout cad
circuit optimisation
logic cad
network routing
 
Description We propose a timing-oriented logic optimization technique called the Generalized De Morgan (GDM) transform, that integrates gate resizing, net buffering and De Morgan transformation. The contribution of our work lies in the integration of the three techniques, allowing them to interact at a much finer level of granularity than would be otherwise possible. This produces better results than those obtainable by individual techniques like net buffering or gate resizing applied to the circuit in various combinations. GDM transform is also layout-friendly since it does not alter the routing patterns and placement of cells, except possibly some buffer insertions/deletions. Hence it is useful for achieving timing closure in late stages of the design flow. We propose a comprehensive GDM algorithm that (a) determines the best replacement of a gate, possibly with inverted inputs and outputs, along with the best buffering configurations of nets incident on it, and (b) embeds this into a global scheme for optimizing large designs. We have implemented this algorithm in a layout-driven, industrial-strength logic optimization framework, and have successfully applied it to large industrial designs.
 
Publisher IEEE
 
Date 2009-05-19T08:54:22Z
2011-11-28T08:06:09Z
2011-12-15T09:57:29Z
2009-05-19T08:54:22Z
2011-11-28T08:06:09Z
2011-12-15T09:57:29Z
2002
 
Type Article
 
Identifier Proceedings of the 7th Asia and South Pacific Design Automation Conference and the 15th International Conference on VLSI Design, Bangalore, India, 7-11 January 2002, 647-654
0-7695-1441-3
10.1109/ASPDAC.2002.995009
http://hdl.handle.net/10054/1383
http://dspace.library.iitb.ac.in/xmlui/handle/10054/1383
 
Language en