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A practical fast parallel routing architecture for Clos networks

DSpace at IIT Bombay

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Title A practical fast parallel routing architecture for Clos networks
 
Creator ZHENG, SQ
GUMASTE, ASHWIN
LU, ENYUE
 
Subject multistage interconnection networks
parallel algorithms
pipeline processing
telecommunication network routing
 
Description Clos networks are an important class of switching networks due to their modular structure and much lower cost compared with crossbars. For routing I/O permutations of Clos networks, sequential routing algorithms are too slow, and all known parallel algorithms are not practical. We present the algorithm-hardware codesign of a unified fast parallel routing architecture called distributed pipeline routing (DPR) architecture for rearrangeable nonblocking and strictly non-blocking Clos networks. The DPR architecture uses a linear interconnection structure and processing elements that performs only shift and logic AND operations. We show that a DPR architecture can route any permutation in rearrangeable nonblocking and strictly nonblocking Clos networks in O(√N) time. The same architecture can be used to carry out control of any group of connection/disconnection requests for strictly nonblocking Clos networks in O(√N) time. Several speeding-up techniques are also presented. This architecture is applicable to packet and circuit switches of practical sizes.
 
Publisher IEEE
 
Date 2009-06-20T06:37:28Z
2011-11-28T08:25:13Z
2011-12-15T09:57:33Z
2009-06-20T06:37:28Z
2011-11-28T08:25:13Z
2011-12-15T09:57:33Z
2006
 
Type Article
 
Identifier Proceedings of the ACM / IEEE symposium on Architecture for networking and communications systems, San Jose, California, USA, 3-5 December 2006, 21-30
978-1-59593-580-9
http://hdl.handle.net/10054/1543
http://dspace.library.iitb.ac.in/xmlui/handle/10054/1543
 
Language en