Reasoning about digital systems using temporal logic
DSpace at IIT Bombay
View Archive InfoField | Value | |
Title |
Reasoning about digital systems using temporal logic
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Creator |
BAPAT, S
VENKATESH, G |
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Subject |
cad
formal logic temporal logic digital system |
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Description |
Temporal logic is proposed as a medium to describe the timing behaviour of digital systems. Queries on the timing properties of the digital systems can then be answered by testing the satisfiability of appropriately constructed temporal formulae. We suggest ways of improving the standard tableau method of testing the satisfiability of these formulae, and discuss results obtained from an implementation of this method. We claim that this can serve as a designers assistant to debug designs.
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Publisher |
IEEE Computer Society
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Date |
2009-07-18T05:31:57Z
2011-11-28T08:46:17Z 2011-12-15T09:57:45Z 2009-07-18T05:31:57Z 2011-11-28T08:46:17Z 2011-12-15T09:57:45Z 1986 |
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Identifier |
Proceedings of the 23rd ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, 29 June-2 July 1986, 215-219
0-8186-0702-5 10.1145/318013.318047 http://hdl.handle.net/10054/1603 http://dspace.library.iitb.ac.in/xmlui/handle/10054/1603 |
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Language |
en
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