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Reasoning about digital systems using temporal logic

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Title Reasoning about digital systems using temporal logic
 
Creator BAPAT, S
VENKATESH, G
 
Subject cad
formal logic
temporal logic
digital system
 
Description Temporal logic is proposed as a medium to describe the timing behaviour of digital systems. Queries on the timing properties of the digital systems can then be answered by testing the satisfiability of appropriately constructed temporal formulae. We suggest ways of improving the standard tableau method of testing the satisfiability of these formulae, and discuss results obtained from an implementation of this method. We claim that this can serve as a designers assistant to debug designs.
 
Publisher IEEE Computer Society
 
Date 2009-07-18T05:31:57Z
2011-11-28T08:46:17Z
2011-12-15T09:57:45Z
2009-07-18T05:31:57Z
2011-11-28T08:46:17Z
2011-12-15T09:57:45Z
1986
 
Identifier Proceedings of the 23rd ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, 29 June-2 July 1986, 215-219
0-8186-0702-5
10.1145/318013.318047
http://hdl.handle.net/10054/1603
http://dspace.library.iitb.ac.in/xmlui/handle/10054/1603
 
Language en