Automated synthesis of assertion monitors using visual specifications
DSpace at IIT Bombay
View Archive InfoField | Value | |
Title |
Automated synthesis of assertion monitors using visual specifications
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Creator |
GADKARI, A
RAMESH, S |
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Subject |
network protocols
time domain analysis graphical user interfaces computer hardware |
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Description |
Automated synthesis of monitors from high-level properties plays a significant role in assertion-based verification. We present here a methodology to synthesize assertion monitors from visual specifications given in CESC (Clocked Event Sequence Chart). CESC is a visual language designed for specifying system level interactions involving single and multiple clock domains. It has well-defined graphical and textual syntax and formal semantics based on synchronous language paradigm enabling formal analysis of specifications. In this paper we provide an overview of CESC language with few illustrative examples. The algorithm for automated synthesis of assertion monitors from CESC specifications is described. A few examples from standard bus protocols (OCP-IP and AMBA) are presented to demonstrate the application of monitor synthesis algorithm.
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Publisher |
IEEE Computer Society
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Date |
2009-08-17T04:38:09Z
2011-11-28T08:49:17Z 2011-12-15T09:57:48Z 2009-08-17T04:38:09Z 2011-11-28T08:49:17Z 2011-12-15T09:57:48Z 2005 |
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Identifier |
Proceedings of the Conference on Design, Automation and Test in Europe, Munich, Germany, 7-11 March 2005, 390-395
0769522882 10.1109/DATE.2005.74 http://hdl.handle.net/10054/1617 http://dspace.library.iitb.ac.in/xmlui/handle/10054/1617 |
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Language |
en
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