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Evaluation of pausible clocking for interfacing high speed IP cores in GALS framework

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Title Evaluation of pausible clocking for interfacing high speed IP cores in GALS framework
 
Creator MEKIE, JOYCEE
CHAKRABORTY, SUPRATIK
SHARMA, DK
 
Subject asynchronous circuit
data communication
digital integrated circuit
network synthesis
 
Description Pausible clocking schemes have been proposed by GALS architects as a promising mechanism for reliable data transfer between synchronous modules fed by low-speed independent clocks. In this paper, we argue that existing schemes are not well-suited for interfacing high-speed IP cores with large clock-distribution tree delay and high communication rates. We propose an alternative interface circuit design for such IP cores that works with partial handshake between communicating modules and minimizes the performance penalty of the sender and receiver. Our circuit, unlike pausible clocking, has a small probability of failure.
 
Publisher IEEE
 
Date 2008-12-15T10:29:52Z
2011-11-28T09:19:38Z
2011-12-15T09:58:11Z
2008-12-15T10:29:52Z
2011-11-28T09:19:38Z
2011-12-15T09:58:11Z
2004
 
Type Article
 
Identifier Proceedings of the 17th International Conference on VLSI Design, Mumbai, India, 5-9 January 2004, 559-564
0-7695-2072-3
10.1109/ICVD.2004.1260978
http://hdl.handle.net/10054/319
http://dspace.library.iitb.ac.in/xmlui/handle/10054/319
 
Language en