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Microstrip equivalent parasitics modeling of RFIC interconnects

DSpace at IIT Bombay

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Title Microstrip equivalent parasitics modeling of RFIC interconnects
 
Creator MUKHERJEE, JAYANTA
YOUNG-GI KIM
INWON SUH
ROBLIN, PATRICK
YAO-CHIAN LIN
WAN RONE LIOU
BAGHINI, MS
 
Subject cmos integrated circuit
integrated circuit interconnections
microstrip circuit
microstrip lines
 
Description We experimentally demonstrate a modeling methodology for inductive parasitics of RFIC interconnects. The method exploits the equivalence between a microstrip line and the cross section of a multi metal layer CMOS fabrication process. The proposed model is applied on an oscillator fabricated in a standard 0.18 mum mixed mode CMOS process. We compare the experimental results of the phase noise of the oscillator so fabricated with the simulation results using the microstrip equivalent model for the interconnects. The simulation and experimental results match very closely.
 
Publisher IEEE
 
Date 2009-01-01T03:47:49Z
2011-11-28T00:58:28Z
2011-12-15T09:58:16Z
2009-01-01T03:47:49Z
2011-11-28T00:58:28Z
2011-12-15T09:58:16Z
2007
 
Type Article
 
Identifier Proceedings of the 50th Midwest Symposium on Circuits and Systems, Montreal, Canada, 5-8 August 2007, 435-437
978-1-4244-1175-7
10.1109/MWSCAS.2007.4488623
http://hdl.handle.net/10054/517
http://dspace.library.iitb.ac.in/xmlui/handle/10054/517
 
Language en