Microstrip equivalent parasitics modeling of RFIC interconnects
DSpace at IIT Bombay
View Archive InfoField | Value | |
Title |
Microstrip equivalent parasitics modeling of RFIC interconnects
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Creator |
MUKHERJEE, JAYANTA
YOUNG-GI KIM INWON SUH ROBLIN, PATRICK YAO-CHIAN LIN WAN RONE LIOU BAGHINI, MS |
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Subject |
cmos integrated circuit
integrated circuit interconnections microstrip circuit microstrip lines |
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Description |
We experimentally demonstrate a modeling methodology for inductive parasitics of RFIC interconnects. The method exploits the equivalence between a microstrip line and the cross section of a multi metal layer CMOS fabrication process. The proposed model is applied on an oscillator fabricated in a standard 0.18 mum mixed mode CMOS process. We compare the experimental results of the phase noise of the oscillator so fabricated with the simulation results using the microstrip equivalent model for the interconnects. The simulation and experimental results match very closely.
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Publisher |
IEEE
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Date |
2009-01-01T03:47:49Z
2011-11-28T00:58:28Z 2011-12-15T09:58:16Z 2009-01-01T03:47:49Z 2011-11-28T00:58:28Z 2011-12-15T09:58:16Z 2007 |
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Type |
Article
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Identifier |
Proceedings of the 50th Midwest Symposium on Circuits and Systems, Montreal, Canada, 5-8 August 2007, 435-437
978-1-4244-1175-7 10.1109/MWSCAS.2007.4488623 http://hdl.handle.net/10054/517 http://dspace.library.iitb.ac.in/xmlui/handle/10054/517 |
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Language |
en
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