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VLSI implementation of artificial neural network based digital multiplier and adder

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Title VLSI implementation of artificial neural network based digital multiplier and adder
 
Creator RANADE, RANJEET
BHANDARI, SANJAY
CHANDORKAR, AN
 
Subject cmos digital integrated circuit
vlsi
digital arithmetic
multiplying circuit
 
Description This paper describes a technique to realize a novel digital multiplier using Artificial Neural Network (ANN). It proposes a generalized `Energy Function' for multiplier and its hardware realization by combining conventional digital hardware with a neural network. The design of neurons, extended range active loads and the digital multiplier are described in this paper along with the simulation results .
© IEEE
 
Publisher IEEE
 
Date 2008-12-22T05:44:36Z
2011-11-28T00:48:07Z
2011-12-15T09:58:20Z
2008-12-22T05:44:36Z
2011-11-28T00:48:07Z
2011-12-15T09:58:20Z
1996
 
Type Article
 
Identifier Proceedings of the Ninth International Conference on VLSI Design, Bangalore, India, 3-6 January 1996, 318-319
0-8186-7228-5
10.1109/ICVD.1996.489620
http://hdl.handle.net/10054/443
http://dspace.library.iitb.ac.in/xmlui/handle/10054/443
 
Language en